Solved Problem In Control System By Jairath Pdf Free 144
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Essentially all silicon wafers for IC applications are grown by the Czochralski (CZ) method. An important difference between this method and the Floating Zone (FZ) method is that the silicon melt is contained in a quartz crucible. The main result of this is that oxygen from the crucible is unavoidably dissolved into the molten silicon and incorporated in the solid crystal ingot in rather high concentrations. For a variety of reasons, the rather low mobility of oxygen in silicon being one, this excess oxygen can precipitate homogeneously, that is, at arbitrary sites, in a silicon crystal. This can occur during the cooling of the crystal during growth and in subsequent wafer heat treatments during use. Oxygen precipitates in bulk, or interior, of silicon wafers create disorder which can effectively lower the barrier for the subsequent precipitation of metals just like disorder on the wafer surface. The potential for using bulk oxygen precipitates as a gettering mechanism was first proposed in 1977  although the mechanisms were not clear at the time. In fact, it is known  that even very tiny oxygen precipitates at very early stages of growth (too small to observe by the conventional etching techniques normally used to see them) can result in energy barriers lower than that of a free surface and thus offer the potential for very effective suppression of surface precipitation and thus gettering. On the surface of things, the use of oxygen precipitates to control metal precipitation is a very attractive idea. A huge effort has been extended in the years since the realization of this effect to harness the potential of bulk oxygen precipitates to manage metal contamination. Such an approach to gettering is called internal gettering (IG).
The IG approach clearly side-steps the issues of particle contamination and damage longevity. But the use of oxygen precipitates as a gettering system can be a dangerous plaything. The engineering challenge is to insure that sufficient densities of oxygen precipitates are robustly and reliably produced in arbitrary IC processes and that a surface layer free of oxygen precipitates (a denuded zone) is produced in the wafer during the processing of the wafer. The denuded zone is required to avoid the presence of oxide precipitates in the near surface device layer in order to avoid detrimental effects of oxygen precipitates themselves. This is usually achieved by causing the dissolved oxygen in the wafer to out-diffuse at high temperature prior or during the nucleation of the oxygen precipitates in the bulk. This is often a costly additional process step which serves no other purpose than to prepare the wafer for use. A sufficient density in the bulk of the silicon wafer is required. This is to insure that, once metal precipitation starts at the oxide precipitate sites, these volume distributed sinks for metal diffusion are of a sufficiently high density to insure that a sufficient suppression of the metal concentration near the front surface in order to suppress metal precipitation there. It is known that oxygen precipitate densities of about 1-5 x 10 8 cm-3 are required for this [5,6]. An example of an ideal depth distribution of oxygen precipitates for gettering purposes is shown in Figure 3. Illustrated is a defect etched cross-section of a processed silicon wafer. The surface of the wafer is at the top. The depth of the defect free denuded zone is about 80 microns and the bulk density of oxygen precipitates is about 8 x 10 9 cm-3.
The engineering challenge to reliably produce such internal gettering structures has often proven to be illusive or expensive, or both. The general problem of the physics of the precipitation of oxygen in silicon has proven to be hugely complex and remains a still wildly unsatisfactorily resolved problem. In the 20 or so years since the discovery of the IG effect in silicon wafers, many scientists and engineers have struggled with the problem of precisely and reliably controlling the precipitation of oxygen in silicon which occurs during the processing of wafers into integrated circuits. This has been met with only partial success in the sense that the "defect engineering" of conventional silicon wafers is still, by and large, an empirical exercise. It consists largely of careful, empirical tailoring of wafer type (oxygen concentration, crystal growth method, and details of any additional pre-heat treatments, for example) to match the specific process details of the application to which they are submitted in order to achieve a good and reliable IG performance. In conventional silicon wafers the resultant oxygen precipitate density profiles are wildly dependent on the details the crystal growth process (primarily crystal cooling rates), the oxygen content of crystals and the details of the IC process to which the wafers are submitted. As a result, an entire industry-within-an-industry has sprung up built around attempts to control and tailor the oxygen precipitation performance of silicon wafers to specific processes. A large proportion of the complexity (and hence cost) of the manufacture of silicon wafers is centered on the specification and control of oxygen concentration and its behavior. Once a process is known to work for a given application a kind of process rigidity sets in. The potential for cost saving process improvements are reduced. Armies of expensive applications engineers and their counterparts at IC houses work on the tailoring of oxygen concentration and crystal growth processes to meet the needs of specific silicon applications. These are costs which the industry can no longer bear.
Temperature is primary factor that controls the strength of the silicon wafer, and this must be taken into account when setting furnace push/pull and temperature ramping conditions. The strength of the wafer decreases significantly at its temperature is increased from 750°C to 800°C. If wafers are pushed into or pulled from a furnace tube set at 750°C, wafer slip is almost never a problem, but if they are pushed or pulled with the tube set at 800°C, slip is almost always a problem. The strength of the wafer decreases further as its temperature is increased further. To prevent wafer slip during furnace temperature ramping, it is necessary to use lower and lower ramping rates for higher and higher temperature ranges. Recommended ramp rates for 200 mm wafers are given in "How to Prevent Furnace Slip." Smaller diameter wafers can be ramped slightly faster, but 300 mm wafers must be ramped more slowly.
The denuded, or oxygen precipitate free, zone in MDZ® is a real one in the sense that the near surface density of oxygen precipitates is effectively zero. In other approaches to the problem this is not necessarily the case. For example, when oxygen precipitation enhancement is attempted at the crystal growth level, as in the case of nitrogendoped silicon, no "real" denuded zones are possible. The high temperature oxygen out-diffusion treatments which are applied to such wafers result in an "apparent" denuded zone only. The grown-in precipitates are not themselves dissolved. The oxygen concentration reduction near the surface merely restricts the size of precipitates there; at some point they cannot be detected by simple etching. But the density of oxygen related defects, in fact, remains the same -- all the way to the wafer surface. Crystal-growth based precipitation enhancement schemes increase the constraints placed on the crystal growth process. MDZ® frees the crystal growth process to be whatever it needs to be to decrease costs.
D-defects -- Very small voids in Silicon formed by agglomeration of vacanciesDIBL -- Drain Induced Barrier LoweringDIC -- Differential Interference ContrastDL -- Diffusion LengthDMOS -- Double-diffused MOSDOE -- Design of ExperimentsDOF -- Depth of FocusDRAM -- Dynamic Random Access MemoryDSOD - Direct Surface Oxide DefectDSP -- Double Sided PolishDZ -- Denuded Zone (depth measured from the surface that is free of oxygen precipitates and which is denuded of interstitial oxygen (by out-diffusion))Defect Free Region: The linear distance from the frontside wafer surface to the depth of the first bulk defect.Degree: Unit of measuring angles when orienting an ingot.Design of Experiments (DOE): Method to design, run and analyze an experiment to maximize information and minimize testing.Diameter: Straight-line measurement drawn through the center of a circle or sphere from one side to the other.Diffusion: A method of doping or modifying the characteristics of semiconductor material by "baking" wafers of the base semiconductor material in furnaces with controlled atmospheres of impurity materials.Diffusion Length: The distance a front side free-electron or hole can travel through a crystal. This is proportional to the Lifetime of the crystal.Dislocation: A class of one-dimensional, or line defects in silicon crystals.DNZ (Denuded Zone Depth): The linear distance from the frontside wafer surface to the depth where the defect density appears nearly uniform.Donor: Atom, usually an impurity in silicon, that acts as an electron source. It contributes an extra electron to the crystal structure. Most common is phosphorus.Dopant: Element added to silicon decreasing its resistivity. Silicon, by itself does not conduct electricity. Boron is usually used for p-type and phosphorus is usually used for n-type.Doping or Dopant: Chemical impurities added to polysilicon which will yield either n- or p-type silicon, depending on the specific dopant used.
LAD -- Large Area DefectLg -- Transistor Gate LengthLLS -- Localized Light ScatterersLLPD's -- Large Light Point DefectsLPCVD -- Low Pressure Chemical Vapor DepositionLPD's -- Light Point DefectsLPD-E -- Light Point Defect, class E (a KLA-Tencor SP1 defect class)LPD-N -- Light Point Defect, class N (a KLA-Tencor SP1 defect class)LPD-S -- Light Point Defect, class S (a KLA-Tencor SP1 defect class)LPE -- Liquid Phase EpitaxyLSE -- Latex Sphere Equivalent particle sizeLSI -- Large-scale IntegrationLSTD -- Laser Scattering Tomographic DetectionLTO -- Low Temperature OxideLapping: Process to remove controlled amounts of silicon from the slice using a lapping compound. This process removes saw damage and positively impacts the slice's flatness.Laser mark: Method of identification required by some customers. Series of letters and numbers inscribed onto the wafer by laser.Lifetime: The average time a free-electron or hole can exist in a crystal, measured in seconds. Lifetime may vary within a crystal: bulk lifetime within the crystal and surface lifetime at, of course, the surface.Linear Thickness Variation: Thickness variation within a slice whose front and back surfaces can be represented by two, nonparallel planes.Local or Site Flatness: Flatness of specifically defined areas on the slice.Lot: Group of wafers going to the same area with the same identities and are to be processed together.Low Temperature Oxide (LTO): Sealant to keep the dopant in the wafer when it goes through the Epi process. It is applied in Furnace/Enhanced Gettering Area.LPCVD: Low Pressure CVD, deposits a layer of polysilicon to the wafer, later removed by polishing. A backside layer can act as a gettering agent.LPD: Light Particle Defect, sometimes known as particles. 2b1af7f3a8